<?xml version="1.0" encoding="utf-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	>
<channel>
	<title>Comments on: Insomnia</title>
	<atom:link href="http://www.snell-pym.org.uk/archives/2008/04/26/insomnia/feed/" rel="self" type="application/rss+xml" />
	<link>http://www.snell-pym.org.uk/archives/2008/04/26/insomnia/</link>
	<description>Sarah and Alaric Snell-Pym living in interesting times</description>
	<pubDate>Wed, 19 Nov 2008 23:44:49 +0000</pubDate>
	<generator>http://wordpress.org/?v=2.5</generator>
		<item>
		<title>By: @ndy Macolleague</title>
		<link>http://www.snell-pym.org.uk/archives/2008/04/26/insomnia/#comment-73383</link>
		<dc:creator>@ndy Macolleague</dc:creator>
		<pubDate>Wed, 30 Apr 2008 14:53:19 +0000</pubDate>
		<guid isPermaLink="false">http://www.snell-pym.org.uk/?p=768#comment-73383</guid>
		<description>&lt;p&gt;wrt 3:
I think that there is already a trend towards this sort of thing in the HPC sector. There are already companies offering FPGA products that sit on the PCIe bus and possibly even the hypertransport but and act as streaming processors. It's a small jump to have a Dynamic DIMM where, between the CPU's write and read from a given address, the DIMM itself performs a calculation on the data.&lt;/p&gt;

&lt;p&gt;The main hurdle is integrating it with peoples' existing system: writing OS drivers that can drive these things and supplying people with the tools to write and customise their own algorithms. How does the ARGON architecture stand up in the face of running standardised code on conventional CPUs as well as FPGAs? Writing effective FPGA "compilers" is an interesting topic at the forefront of computer science research.&lt;/p&gt;
</description>
		<content:encoded><![CDATA[<p>wrt 3:
I think that there is already a trend towards this sort of thing in the HPC sector. There are already companies offering FPGA products that sit on the PCIe bus and possibly even the hypertransport but and act as streaming processors. It's a small jump to have a Dynamic DIMM where, between the CPU's write and read from a given address, the DIMM itself performs a calculation on the data.</p>

<p>The main hurdle is integrating it with peoples' existing system: writing OS drivers that can drive these things and supplying people with the tools to write and customise their own algorithms. How does the ARGON architecture stand up in the face of running standardised code on conventional CPUs as well as FPGAs? Writing effective FPGA "compilers" is an interesting topic at the forefront of computer science research.</p>]]></content:encoded>
	</item>
</channel>
</rss>
