Cyber Punk London (by )

The Old and the New London

Years ago (over a decade actually) Alaric tasked me with illustrating two Role Playing Games he had written. I have been steadily working on them and part of that is finding suitable visuals to construct the very specific images needed. So I often trail around cities taking images of cyber punk type stuff and the fanciful - the weekend allowed me to sneak some pics 🙂

Ciggy bin face

Our cities are full of unexpected finds like this ciggy bin face - it is obviously a droid from Alpha Centuri and is fed up with people putting burning leaves into it's eye sockets!

Interesting micro structure in amongst the buildings London

Little micro structures hide, clinging to the larger buildings around them as if we truly are creating a jungle of a different type - covergent evolution, lies at the heart of this one 🙂

Pipes on buildings in London

There were so many great shapes and geometries but I had limited time as we were lit. rushing from the station to meet our friends. I want to go back and spend another creative weekend in London, catching as many of the little hidden textures as I can!

Looking up through the sky scrappers to a patch of sun light

As beautiful as the buildings are, there is also something menacing about some of them, they loom in and block out the light. But if you look hard enough it is still there, defiant of the giants that rise on metal frames.

A parasitic tower hiding in the sky scrapers London

Parasitic towers cling to their host buildings gloaming in reflected sunlight, the light was sunset light and was thick and golden, tinged with surrealism as the cities lights mingled with it.

Buildings reflecting buildings London

The city is a labrynth, including confusing and distorting reflection. They buildings are glass coated, they shine and reflect and capture each other's images, it can be hard to tell what is a building, and what is a reflection of a building on a building or a building within a building.

Steal and Glass rainbow reflection

The steal and glass and light created metallic rainbows and an eye rolling husband who was trying to make sure I did not walk off of steps or in front of cars as I was so captivated by the scenes.

Building geometry London

The building vary, some are angular and sharp and others are soft and curvy and some are curvy and angular but modular and it is a landscape of geometry.

Metal imitates bone and nerve

Again the shapes and angles begin to suggest something organic - in this case back bone and central nervous system - it made me think on what would happen if metal suddenly became alive - what sort of creatures would our cities spawn?

The scales of the gerkin London

Many patterns, textures and ornamentation where present and just waiting for me to capture them, the gerkin looks like glass scales, arching off into the distance. I am also starting a photo study of texture this spring and the buildings were a surprising source of such imagery.

Marshmallow trees and ancient church London

And of course hidden in this new glass and chrome London is an older London, and it cries out for stories and contrasts and has a kind of magic realism. These pictures scream... write us into a story, a poem, a piece on heritage and art... and that is indeed what will happen to these images, they will be appearing on my writing and art blogs in various guises as well as being used for drawing practice 🙂

marshmallow trees and red bricks hiding in glossy london

But really why are there giant marshmallows in these trees? And they were not the only strange and fantastical thing we found - a steampunk macarbe sat in the pub where we met our friends just before heading for curry on Brick Lane - there were clusters of young people preaching or goading or occupying London. There was a religious zing to them and they dressed in threads that were bare for aesthetics rather than worn to unravelling. I could not hear what was being said but they had followers with glassy zeal in their eyes. A passion pulsed in the underbelly but it was a safe fire, a cold fire.

Skeleton Seat The Water Poet London

We had a great meal and catch up with friends but as always I am reminded that my London is erroding, disappearing, I can not say weather this is a good or bad thing but London is bright and over whelming, like a million pieces of brain fire. Confetti of glitz and glam that may well tarnish or burn out in the blink of an eye. The markets are gentrified and hipster zones, interesting but no longer mine. Consumerism as always drives the city forward - this has not been lost on the natives living in all the envrions of London - a city of villages and zones.

Buy Shit graffiti London

Music and Friends (by )

Just at the point where Jean started to take to playing and learning songs for the keyboard/piano, our hammond organ decides to die. We are hoping we can still fix it but it is going to be a major job 🙁

So a friend of ours said we could have an old keyboard of his, it used to be his grandmothers. We picked it up at the weekend with a little musical distraction!

Jean playing with an epic synth keyboard set up

For Jean spotted his epic set up with phone and mic stand and coloured buttons all set up to the computer 🙂

He also has a tank drum from Bali, I love these instruments so he let me have a play and of course that meant Mary had to have a play!

Mary playing with a tank drum from Bali

It was great seeing friends at the weekend - some of whom we've not seen for 3 or 4 years!

Of course after school yesterday my poor old struggling laptop was kidnapped for music recording / song making to happen - this mainly seemed to consist of Jean shouting at Mary for talking over the recording!

Once again I've been amazed by our wonderful friends 🙂

Rainbow Clouds (by )

Yesterday was mad! It took five hours of extra driving to get home thanks to lots of different road works, a detour to th wilds around Oxford due to kids not listening to "go to the toilet now as there wont be any other toilets on the way home" and having to show the nice police that our van only contain kids and no stolen motobikes!

Rainbow Clouds before the night lights

But it did mean we were driving when the rainbow clouds appeared in the sky, the colours haven't really come out that well - possibly as the best angle for colour was not one where I could get a picture and I was in a moving van taking the photos through the windscreen!

Iridescent clouds

I believe this is Cloud Iridescence and was something I have only come across in the last few years when I saw and photographed some green clouds with my phone. Since then I have been seeing it quiet regularly though normally when I am not in a good position to take photographs!

Rainbow Cloud

It's basically little ice crystals in the clouds working like mini prisms and splitting out the colours of sunlight. It's beautiful, I am wondering if it is because our climate is changing that I've only just started seeing it or if it is because I was just really unobservant before?

Extra-Ordinary (by )

Today I feel like a failure, today I feel fat and not ugly so much as plain with frizzy hair and glasses. Today I looked at the things I make and think... they are all a bit naff. Today I am the failed scientist and the untrained artist, today I am FAILURE.

Today I am the stuck at home, non housework doing, burnt cooking mum, I am the can't spell, can't concentrate hack filling in forms to apply for events/jobs that I know wont want me, not daring to apply for the acting roles as I'm too fat, too old, too short, the wrong physical gender, I am the failed to get my kids to the things they want and need to go to, I am the fail parent with a trail of failed careers.

Today I finished knitting DNA, and worked on a mermaids tail, cut out and folded a micro-zine I drew and scanned and made, I helped Mary write a story and she made a cover for it to be a book, Jean helped me find my unfinished knitting projects and I finished the basis for some little easter rabbits. I typed up a poem and ordered polymer clay to make little creatures with. I put away a giant papier mache sculpture I made for the visually impaired and checked that the brain I am making is drying ok, there were piles of paintings I had to move, piles of my paintings - I can't see them as good, I can't compare to the other artists that I see locally, my stuff just... does not quiet cut it and yet... it is the headline picture for the group.

Today I feel like a fraud, I feel like I am pretending to be good, to be amazing, when I am not. I am just me, a lost, lonely little me. A few days ago I performed at a launch event, people came to tell me how animated and full of energy I was, they said they liked my work, the world was full of chances to grab and take and I did... but... I stood outside the venue looking at the door, wondering if I was truly supposed to be there, weather I was an interloper, I had to battle mind doubt dragons to go in and whilst I talk, whilst I feel alive at the creativity around me, I look at the crowd of amazing people and think how wonderful they are and how drab I am. And I feel the press of eyes and the expectation and I want to run, I want to hide, I am the extroverted introvert or introverted extrovert and sometimes I think I have wasted my life.

Today I sit writing this drowning in craft supplies I need to put away, this week I have designed many new workshops covering science, art, writing, specific themes and the environment. My old injuries ache with the clammy cold weather and I long for summer but know I have much to do but I can not stir, my head still rings from the head injury I had coming up to two years ago now and I feel thick, stupid, clogged, my c-section scar is hurting, skin burning and sinus pain is king. It is nothing to the physical pain and discomfort I have suffered in the past, I'm a little inflamed and virally that is all. I fail at not moaning, at not feeling used up and rung out.

Today I think of all the people who have helped me and I know I have failed them and worse I have not always passed the buck, I have been too busy or distracted or lazy. I walk past the homeless and realise that it more than two years ago that I did any proper charity work, even though an event I acted at this month has just raised over £400 for charity, I had to claim my expenses - I have a loan to repay and things I need to get to - I failed at money management - I struggle with numbers now, I did not used to. I had to take the money but not because I would starve because I wouldn't and that makes me wither inside. Am I greedy?

Today I told my husband - I told him how when I write down the things I have done they sound fantastic and great, or brave and selfless - when I know it wasn't like that, it was clutching at straws, it was trying stuff, it was itself often failure. My life has twisted and turned and looped da looped and I am giddy.

Today he told me I am extraordinary and that most people - are not. He told me that people are in awe of my work but these words hurt and puzzle. He gave examples and I am like "no that is just because they have had to survive differently, they want to do stuff, creative stuff, science stuff." And then I was angry about how their potential is being lost, how my potential was lost, about how my husband would be the better home maker and can't be, how society traps people in rolls and classes and demographs.

Today I survived, I live and so does my family, and for that I am truly in awe and fearful of a harsh and unrelenting world. But sometimes... sometimes survival is not enough and that is only because I am lucky, I have capacity, I have safety nets, I have family and friends and love and food and shelter. I am higher up the triangle of needs - but that should not be the case. Potential maximium should be achievable for all, with no judging as to what that is, no expectations of what a successful life is, no squinting and muttering when a sideways corse is taken. Failure should not be seen as well... failure. It is the experimenting, the living of life, it is were the discoveries are made, if you don't try you can't fail, but if you don't fail have you ever really tried?

Today is not today anymore, today is now tomorrow and I feel the ideas scritching in my brain, they have been gone a long time, I have to rest lots to let my brain heal - it healed enough to give me ideas again. Proper new fresh ideas, but my health has always been shoddy and I have lost so much time, and I can't go fast, I can just be. So I pool and collect the ideas, and hope they will get their day. Somedays they erupt into the world and the world laps them up, other days... not so much and I gather them back in for another try, on another day.

Today is new, I still feel hollow, but that will pass, it always does, and the void will be filled with colour and patterns and thoughts and then I'll accidently create a thing or things or a thing of things. Until then there is hugs and coffee, and admin.

Processor architecture (by )

The current state of the art in processor design seems to be a reasonably complex instruction set, which is interpreted by a thing that translates it into a series of more primitive instructions which are then fed into some kind of multiple-issue pipelined thingy with speculative execution. You know, the kind of stuff x86 has been since the 386. 64-bit instructions, vector SIMD instructions, lots of cores and all that are just variations on the theme.

I'm sure this is a local maximum in the space of processor designs. So few of the transistors on each chip seem to be actual ALU doing something useful. All this translation and pipeline control seems to be a lot of logic that's just adapting to the impedance mismatch between the ALUs and instruction set...

So, I'm always interested in more exotic processor architectures, and there's two different threads I'd love to explore (as in, design and simulate in an FPGA) if I had time. The common theme is simple control logic; this means you can fit in more ALUs, or wide ALUs and registers, in the same space - or just fit more cores and more cache on the same die.

Zero-operand stack machines

The idea here is to use a stack instead of a register file. This means that instructions just need an operator (eg, "add") as the operands are implicit - the stack always provides the inputs and outputs. This means that the instructions can be very small due to the lack of operands; generally, much smaller than a machine word, so each word loaded can have several instructions in. This can mean that the memory bandwidth required to feed the chip with instructions is reduced; and since the decode and control logic becomes very simple, you can sustain a high clock rate with minimal pipelining, so reducing the memory bandwidth consumed by instruction loads is handy.

That means you can't fit literals or static addresses inside instructions, though, so you need something like a "load immediate" instruction that fetches the next word from the instruction stream and pushes it, rather than treating it as instructions. If an instruction word contains several "load immediate" instructions, then that many subsequent words of instruction stream could be literals!

One example of this approach is a Minimal Instruction Set Computer, but the concept is broader than that. Large instruction sets can be easily supported.

The control logic boils down to loading an instruction word, then treating it as a FIFO of smaller instructions to execute while the next instruction word is loading. Most instructions just engage an ALU circuit hardwired to the top element or two of the stack, whose output becomes the new top of stack. A few might transfer data to/from a memory access unit or a register, including the instruction pointer to change the flow of control. Not many gates are needed to decode an instruction, leading to the short cycle time.

Instructions that can't complete in a single cycle present a problem, though. The use of a stack tends to mean that an instruction depends on the result of the previous instruction, so it's tricky to execute several instructions in parallel and thus make progress in the presence of weighty multiply/divide instructions or memory reads.

I can think of three ways of overcoming that, and you can combine all three:

Multiple stacks

The approach taken by the 4stack processor is to have four stacks, each with its own independent ALU. Each instruction word has an instruction for each ALU in, and they execute in parallel on each clock tick. Presumably, there's some means to transfer results between the stacks - I imagine a bus joining them, an instruction to pop a value from the stack onto the bus, and an instruction to push from the bus. The timings of the bus reads and writes are such that it's possible to have an instruction word with a pop->bus from one stack and push->bus for one or more stacks that do such a transfer in a single cycle.

Due to the synchrony of instructions feeding into each ALU, we can't "stall" an ALU. If one of them executes a weighty instruction or has a cache miss on a memory read, we either stall ALL the ALUs at once, or we mandate that certain instructions are followed by a fixed number of NOPs before another instruction can execute, to allow time for it to complete.

This puts the onus on the compiler to schedule instruction-level parallelism, and means that the compiler needs to know the precise timings (and number of ALUs) of the target CPU - we can't use the same instruction set for a broad range of implementations!

Result registers

Weighty instructions might not put their results straight on the stack; instead, the instruction might cause the inputs to be pulled from the stack and the instruction starts executing. When it completes, the result is latched into a result register, and a later instruction pushes the contents of the result register (stalling if it's not ready yet). This means that the instruction stream can get on with other stuff while the lengthy instructions run. However, it requires such multi-cycle instructions to inherently work differently; and it puts some onus on the compiler to know how many instructions to wait between starting these instructions and trying to access their results for best performance.

Virtual stack

Finally, we can virtualise the values on the stack. A division instruction, for example, might read two actual values from the stack and then push a token that means "Wait for the result coming from division unit 7". If the next instruction is an addition, then it would read that token and (say) a literal value from the next stack position; since one of the inputs is a token it can't execute yet, but it still assigns an addition ALU and loads the literal value. But it tells division unit 7 to, when it completes, push the result into port 1 of addition ALU 3; and it pushes a token that means "Wait for the result coming from addition ALU 3", and so on. Basically, rather than waiting for operations to complete so you can push a value to the stack, you can instead push a reference to an operation in progress; a cluster of ALUs and memory access units connected by suitable buses then becomes a kind of dataflow machine which is fed connections from the instruction stream, in effect taking the condensed zero-operand instruction stream and using it to assign dependencies between instructions, rather than using virtual registers to assign dependencies as in current CPU designs. But this requires the kind of complex control logic that I feel current CPU designs are drowning in.

Transport-triggered architecture

Another way to simplify control logic is to build your CPU as a bunch of modules with input and output ports. Arithmetic and logic operation modules have one or two inputs and a single output; a memory reader has an address input and a data output; a memory writer has address and data inputs and no outputs; registers have an input and an output; and so on.

Each instruction contains a few bits to control whether the instruction executes conditionally on bits from a flag register, then an output port to read from, and an input port to write the result to. The decoding consists of checking the conditional execution flags then either doing nothing, or pushing the input and output port IDs onto two address busses and toggling a strobe line that causes the output port to write its contents to a data bus, and the input port to load from it.

As with the zero-operand stack machines, the instructions are small, so can probably cram several into a machine word - maybe split into groups that share a single set of conditional execution bits, for even more compactness. These instructions are all operand and no operator!

To insert literal values in the instruction stream, one can again have an output port on the instruction fetch module, that when read pulls a literal value from the instruction stream and stops it from being interpreted as instructions.

The output of each module is a register, where a value appears as soon as it's ready and waits until it's read - so there's no need to explicitly store it in a general purpose register. However, the CPU might have a few general-purpose registers anyway to store stuff in, as well as the usual instruction pointer, flags, and machine control registers.

This makes it easy to exploit parallelism; the instruction stream can trigger lots of modules and then come back later to read their output registers. The compiler might need to know the cycles required to do various things and not read the outputs until they're ready, or there might be handshaking on the internal bus so that instructions stall until an output is ready, which makes it easier to deal with things like memory reads that can take widely varying numbers of cycles to complete. Even then, the compiler can still benefit from knowing cycle timings in order to schedule stuff better.

Modules could be pipelined. Rather than having four multipliers, you might have one that you can feed (say) four sets of inputs into and then, later, read the output register four times to get the results. The compiler might need to know how deep the pipeline is to avoid overflowing it with results; or the hardware spec might mandate that up to sixteen multiplies can be pipelined, and put a FIFO on the output register to make up the extra capacity needed beyond the number of pipeline stages it has.

The downside is that the compiler needs to know how many modules there are and what port numbers are wired up to what. This, again, makes it hard to have a single executable that can run on a wide range of implementations of the design.

However, this looks rather like the execution model behind the virtual-stack machine discussed above - so perhaps we could have a generic stack-based instruction set that is executed by a virtual stack to generate instructions for an underlying transport-triggered machine...

Modules could be quite complex; for instance, an index register module might comprise a register coupled directly to a memory access system. By accessing different input or output registers, it could update the contents of the register, or write to the memory address stored in the register, or read from the memory address in the register; and different input/output ports could be accessed that cause it to pre- or post-increment or -decrement the index register at the same time, allowing for efficient operations on contiguous blocks of memory. Also, the internal data bus might be arbitrarily wide, allowing ALUs to operate on, and registers to store, vectors of several machine words; modules that only operate on a single word at a time might sacrifice a few input-port-select bits in their instructions to select which word from the vector on the data bus to read into their input port.

To save on space taken up by literals, we can have a simple module with output ports that produce some useful constants (0, 1, -1); or dedicate a single bit of the instruction to selecting whether the input port number field specifies an input port, or is a literal to just load onto the data bus. An input port number will be much smaller than a machine word, so this will only cater for small literals, but most literals are small and we can fall back onto fetching an entire word from the instruction module for larger literals. We might want to sign-extend a small literal, however.

The data bus might become a bottleneck, but that's OK - we can have several of them, and make the instructions specify an input and output port number for each bus; we then trigger multiple transfers in each instruction cycle. This is very similar to having several instructions in a machine word, except that they execute in parallel rather than serial. We just now need to specify what happens if the same port is read or written by two parallel transfers!


A general theme with many of the above approaches is that the compiler ends up needing to know more about the details of the chip implementation, because the compiler is responsible for more scheduling.

Perhaps this is no bad thing - runtime code generation is becoming the norm anyway, and it would be possible to bootstrap the system by having an initial "minimal instruction set" which is standardised, and allows access to a description of the current chip architecture; the runtime code generator can then be compiled (using a compiler written in the minimal instruction set), and then the processor switched into normal mode. This might even be implemented by having a simple version of the stack architecture as a front-end processor that starts executing code while the main CPU is dormant; it then has an instruction that hands an initial instruction pointer value to the dormant main CPU and starts it up. Multicore systems would need only one front-end processor to bring the whole system up!

Another approach might be to have a transport-triggered architecture with a small set of guaranteed modules available at well-known port numbers in every implementation, with variation occurring in the rest of the port-number space. But this requires the instruction format to have enough bits for the port numbers to allow for the largest imaginable processor, leading to unnecessarily wide instructions for smaller devices. Perhaps this can be handled by having the instruction decoder support both standard narrow instructions and implementation-specific wider instructions, again starting off in standard mode and allowing switching to wide mode once the processor definition has been read and used to compile the compiler that can exploit the full capabilities.

Either way, I think that future processor architectures might be more tightly coupled to the compilers than we're used to.

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