Digital logic progress (by )

Yay! The core of the logic simulator is getting pretty near completion now. I've been working on a project that involves glacial compilation times, which give me 5-10 minute blocks every 30 minutes or so, so I've been typing in the list of logic simulator changes I had written in my notepad. It now handles the thorny issues of rapidly-changing drivers and all that I spoke of in the last posting, plus I've tidied up the way probing circuit activity and injecting test inputs works. Previously, I had signal injector and logic probe devices that could be attached to lines, but this meant they affected the transmission line model and altered the timings of the circuit under test... I've since made tracing and signal injection an inherent property of the line, so it has no side-effects. This also means that the signal injector can override an existing signal on a line; previously, injecting a 1 into a line that was reading 0 due to another driver would have given an error, but now a line being 'injected' will just do as its told and ignore the drivers.

Also, the output tracing now outputs Value Change Dump files as well as plain text output, so I can view the traces in GTKWave or other apps that support the VCD format. The plain text output format is better than a wave viewer for busses, since it helpfully shows which bits have changed:

    00000221: A:

...that indicates that the least signifcant two bits of the A bus settled to 0, 221 picoseconds after time started.

In graphical form, that's:

Graphical form is great for single lines, and for emphasising timing relationships, though.

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1 Comment

  • By andyjpb, Sat 1st Jul 2006 @ 2:04 pm

    Can you implement a PAL using a ROM?

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