Father’s Day! (by alaric)

Yesterday was Father's Day in the United Kingdom.

Now, Jean doesn't know this since she only just approaching ten month's old, but (perhaps due to recovering from illness) she was very affectionate today and always seemed to want me to pick her up and hold her, then was all fun and happy when I did. So I felt very loved 😉

Laryngotracheobronchitis (by alaric)

Poor little Jean! She was well recovered from her past viral infection, but a few days ago she started to drool excessively, went off her food, and became generally unhappy. We thought at first that she was just having more teeth break through her gums, which would have those effects, but she then started coughing, sleeping lots, she'd lost her voice, was hardly drinking any milk or water, and some spots that had begun to appear on her lower lip (where all the drool was running down) turned into nasty big red ones.

So today we phoned NHS Direct, who said that she sounded like she had croup, so we should expose her to steamy atmospheres. They also said they would contact the local out of hours doctor (our local surgery not being open today), who would ring us back soon.

So they rang back, and said they'd like us to bring her down to them to be looked at, if we could; after all, various other things have similar symptoms to croup, that can be a lot worse.

After a short wait, she was seen by a doctor, who summoned a colleague who specialised in children, and they said that it did indeed appear to be croup, but the one thing they couldn't safely check for was Epiglottitis since, if it was that, poking around in her airway to take a look might cause it to spasm, choking her. So they sent us off to the children's unit at a bigger hospital.

After some form-filling with a nurse, having Jean weighed and her vital signs checked, we were seen by a specialist who gave her a thorough examination, and pronounced that she almost certainly just had croup. He then had to go because of a shift changeover, so after a bit more waiting, another specialist came and said that he agreed, and that the nasty spots were probably Herpes. Sarah panicked a bit at this since she'd only heard of herpes as a sexually transmitted disease, and didn't realise it was the common coldsore, but that was soon cleared up!

So after even more waiting, they gave her some steroids to help reduce the swelling in her throat, and packed us off home.

Phew.

The NHS doctors and nurses we spoke to were lovely; noticeably different from the experiences we'd had in London! From the NHS direct phone people to the out of hours doctors at Stroud Hospital (which, alas, is currently fighting potential cutbacks), and the Children's Centre at Gloucester Royal Hospital, even though we did have to wait a long time for the senior doctor to come and see us!

Digital logic simulation (by alaric)

For a while, I've been considering moving into the soft IP market - designing logic circuits that can be used as modular black boxes in designing circuits for use in FPGAs or ASICs.

However, developing such soft IP blocks can be a challenge; they need testing and debugging. You can get an FPGA development board and put your designs into a chip along with test logic to run them through their paces, but it can be hard to inspect the internal signals that way. Or you can simulate them in software.

So, obviously, I'm going down the software route. Thing is, most digital logic design software has you specify the logic in Verilog or VHDL, neither of which I fancy, for many reasons.

So I've taken to writing my own; one where the design is input as a hierarchial netlist, an actual description of how a circuit would be wired rather than an abstract description of its behaviour. It's designed for purely digital logic, and optimised for speed and ease of debugging.

Currently, since I've yet to write an input driver, circuits and test inputs are set up in C++ source code, but before long there'll be a mini language for setting up circuits and test inputs. For debugging, I've defined a logic probe device that can examine a number of named input lines, or a bus; whenever one of the lines changes the change is detailled, and the new state of the entire bus displayed. Next, I'll define a trap capability, where logic probes can be told to suspend simulation in specified circumstances and give a command prompt, from which the states of lines, busses, and devices can be examined, and test signals injected.

The data model of the system is quite simple; a line is connected to any number of device outputs and inputs. Each device output has a state - 1, 0, ? (undefined), or Z (high impedance). The overall state of the line is ? if any output driving it is ?, or there are outputs driving it with 1s while others are driving it with 0s (in this situation it outputs an error message, too, since that condition can damage devices). If all the outputs driving it are Z, then the overall state is also ?; and if the outputs driving it are a mixture of 1s and Zs, or 0s and Zs, then the overall state is 1 or 0, respectively.

Whenever the overall state of a line changes, it notifies all the devices that have inputs connected to the line.

The system is driven by a scheduler. Devices schedule changes to their outputs at specified times in the future. A device cannot just change an output from 0,1,or Z to any other state - when a device asks to chane its output, what actually happens is that at the specified time the output changes to ? then, a little later, it changes to the desired value, modelling transmission line effects in the line. The delay consists of a small basic delay, plus a second delay factor times the number of device inputs driven by that line, to model the capacitance of all those transistors.

When a device's inputs change, it is notified - if lots of inputs change at the same point in time, it is notified just once, for efficiency (think about 64-bit data busses). The device then figures out if any of its outputs need to change, and if so, schedules changes at suitable times in the future, thus allowing for gate delays.

So far I've implemented an AND-gate device, as the quick and simple test, then I went on and implemented a static RAM. This is much more complex, especially when one considers the effect of timing and inputs having undefined states. The RAM device signals an error if the write line goes high while any address or data lines are undefined, so you need to make sure the address and data busses have stabilised before asserting that write, then when you drop the write line, you need to make sure it's had time to become 0 before removing the address and data signals, since when the write input is ? the RAM device considers that it might be writing.

Likewise, when reading, if the read line or address inputs are undefined, the data outputs are, too.

The point of all this is to make the simulator handle the messy details of logic being pushed with high clock rates. If you try and run things too fast, then you get undefined signals appearing in the wrong places because lines haven't had time to settle before they're needed, and you get errors flagged. With it, I'll hopefully be able to do quite accurate timing models of digital logic - a prerequisite for things like asynchronous microprocessors!

And, yes, when I've finished implementing the simulator (with the circuit input file parser, test input signal parser, VCD file output from the logic probes so the results can be viewed in nice graphical signal viewers, the interactive command line, and a wide range of devices - all the usual logic gates, every type of flip-flop, multiplexers, demultiplexers, and logic blocks like ALUs) - I'll make it open source!

Disturbing dream (by alaric)

Last night, I dreampt I was having a heart attack - horrid pains in my left arm, then I was taken to a hospital and wired into monitors and had a drip inserted, again into my left arm - then I woke up to find that I'd fallen asleep with my left arm bent into an uncomfortable position and it was in agony!

It always fascinates me, how the human mind manages to weave external stimuli into our dreams like that. The classic case is when somebody is shouting at you to wake up or an alarm clock goes off, and your brain weaves it into your dream for a few seconds before you come round...

My weekend (by alaric)

Friday night - worked until about 10pm, getting things done that were meant to be done for Friday.

Then helped pack and prepare to go into London, a 3 hour drive. Sarah's choir reunion starts at 9:45am tomorrow.

Not sure what time we set off, but I remember leaving a service station at about 3am after stopping for a nap because I was starting to nod at the wheel, but I had barely fallen asleep when I was awoken by Sarah's parents ringing her on her mobile, and found my leg had gone dead from trying to sleep curled up on the driver's seat.

I slept in at Sarah's parent's place, but then had to get up in order to go and buy some baby milk powder for Jean, since there was none there. The little nearby chemist turned out to be shut so I walked back and took the van to a large supermarket, braved the Saturday morning queues, and then brought it back. I spent some time fruitlessly trying to fix Sarah's mother's computer which had come down with Microsoft Windows Goes Very Slowly disease, but there were no obviously out of place malware processes running, and it's slow right from the very earliest stages of booting. Then I managed to grab a couple of hours to myself to do some shopping (a shiny thing to put across the windscreen of the van when parked to prevent it from becoming a solar oven, and part of a wedding anniversary present for my wife), and to go for a walk, before picking up Sarah's brother and going to the choir concert that evening. Then to bed.

Then up early Sunday to pack all of our stuff away and go on a delivery mission of various things to various people as we crossed London back towards home, then get home, do work that needs to be done by Monday, then to bed, now at 1:30am. To be up about 7:30am tomorrow morning to take Jean to nursery, then for a conference call to start the next week of work.

Zzzzzz.....